Computer system performance, and thus the size and complexity of the data processing applications that a computer system is capable of adequately operating, depends strongly upon the operating performance of its integrated circuits components, especially the central processing unit (e.g., the microprocessor) and the memory sub-systems. Significant effort continues to be made toward improving the speed of integrated circuit components, such speed measured as cycle times and access times. As these times reduce, especially for such devices as extremely fast access time static random access memories (SRAMs), the time required to drive data output terminals from one state to another is becoming a more significant portion of the overall cycle or access time of the circuit.
As is well known in the art, the output terminals of integrated circuits implemented in a system generally are connected to other integrated circuits by way of conductive circuit board lines. A common arrangement is for several integrated circuits to be interconnected by way of a bus. The load presented by such conductors, including its resistance and capacitance and that of the other integrated circuits connected thereto, can be quite significant. For example, most memory circuit access times are specified for a capacitive load of on the order of 30 to 100 pf. It is therefore common practice to fabricate the driver transistors in output buffers to be as large as possible.
The extremely fast switching provided by large driver transistors generate significant transient noise, however, coupling to power supply and ground lines. Furthermore, since modern computer systems communicate up to thirty-two bits of digital information in parallel, many integrated circuits simultaneously present data at from eight to thirty-two output terminals. The level of transient noise generated by multiple output circuits is, of course, greatly increased in the case where multiple output terminals simultaneously switch from the same state to the opposite state over a brief (less than 10 nsec) interval. Indeed, if all but one of the output terminals switch in the same direction, sufficient noise may couple to the remaining non-switching output terminal to cause a false state thereat.
Referring now to FIG. 1, an example of an output driver circuit which is particularly suitable for multiple output modern SRAM integrated circuits will now be described. The output driver circuit of FIG. 1 is described in copending application Ser. No. 601,288, filed Oct. 22, 1990, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by reference. In the arrangement of FIG. 1, each data terminal D.sub.0 through D.sub.n is driven by a CMOS push-pull output driver of p-channel pull-up transistor 12 and n-channel pull-down transistor 14. The gate of each pull-up transistor is driven by NAND function 20, and the gate of each pull-down transistor is driven by NOR function 22. Each NAND function 20 and NOR function 22, for each data terminal D, receives a data signal on an associated data line DATA, and also receives a common disable signal on line OD (and its complement OD.sub.13 for NAND functions 20). As described in said copending application 601,288, common resistors R5 through R8 are provided through which the NAND functions 20 and NOR functions 22 for the multiple data terminals D are biased to V.sub.cc and ground (i.e., the power supply and ground nodes of NAND and NOR functions 20, 22, respectively, for all data terminals D are connected at common nodes PNAND, GNAND, PNOR, GNOR). This construction provides for control of the switching speed of the outputs, and thus the noise, in a particularly efficient and effective manner.
In operation, a high logic level on line OD (and thus a low logic level on line OD.sub.13) will cause each of NAND functions 20 and NOR functions 22 to turn off their associated driver transistor 12, 14, respectively, thus placing their associated data terminal D in a high impedance state. Conversely, a low logic level on line OD (and corresponding high logic level on line OD.sub.13) allows the state of the associated data line DATA to determine the output state. The circuit of FIG. 1 has been fabricated into actual integrated circuits, and has demonstrated the capability of fully switching the output state of a data terminal D from "rail-to-rail", when fully loaded and in worst case conditions, in 6.5 nsec. The transient noise for the circuit of FIG. 1, considering eight data terminals D switching in the same direction simultaneously, has been observed at the ground terminal to be as high as 1.25 volts. While such performance is quite good for SRAM devices in many applications, these switching speed and noise levels may not be compatible for extremely high speed (sub-20 nsec access time) SRAM devices, particularly with byte-wide or word-wide organization.
By way of background, it is known in the memory circuit art to precharge memory bit lines, by which selected memory cells are connected to sense amplifiers and write circuitry, to a known voltage between memory cycles. Such precharging improves the time necessary for the next selected memory cell to present its data state on the bit lines. An example of a circuit and method for precharging bit lines in an SRAM integrated circuit is described in copending application Ser. No. 627,050, filed Dec. 13, 1990, incorporated herein by this reference. The voltage to which bit lines in memory arrays are precharged may be the power supply voltage, ground, or a mid-level voltage therebetween.
By way of further background, a scheme for precharging an output terminal of a memory integrated circuit is described in Okuyuma, et al., "A 7.5 ns 32K.times.8 CMOS SRAM" IEEE J. Solid State Circ., Vol. 23, No. 5 (IEEE, 1988) pp. 1054-1059. As described therein relative to FIG. 6 of the article, a new cycle is indicated by detection of an address transition and the driving of both the true and complement data lines to a low level. In this prior technique, the low level on both true and complement data lines enables the voltage at terminal OUTPUT to turn on the opposite driver transistor, so that terminal OUTPUT is charged or discharged, as the case may be, to an intermediate level prior to the next data state being presented thereat.
The Okuyuma et al. scheme is subject to several limitations, however, Firstly, the intermediate level is reached by way of a "crowbar" condition (i.e., a DC path between V.sub.cc and ground) during precharge through the circuitry which biases the driver transistors during precharge. In the case where transistor Q1 is turned on during precharge, crowbar current is drawn through the inverter and pull-down transistor biasing the gate of transistor Q1; conversely, crowbar current is drawn through the inverter and pull-up transistor biasing the gate of transistor Q2 when it is precharging the output. In either case, DC current is drawn during precharge. Furthermore, no provision for disabling the precharge condition is present in the disclosed circuit, allowing bus contention to occur in the event of another integrated circuit driving the bus to which terminal OUTPUT is connected. Furthermore, the output driver disclosed in the Okuyuma, et al. article is subject to oscillations due to the feedback connection of terminal OUTPUT to the opposite driver transistor, as there is no apparent provision for turning off the gate driving transistors responsive to the intermediate level being reached at OUTPUT, and also because each of the driver transistors Q1, Q2 can be enabled during a precharge operation. In addition, the circuit disclosed in the Okuyuma et al. article may also be vulnerable to overshoot conditions, depending on the characteristics of the output load.
It is therefore an object of this invention to provide an output driver circuit with improved switching performance.
It is a further object of this invention to provide such an output driver circuit with both high speed switching and also reduced transient noise generation.
It is a further object of this invention to provide such an output driver circuit which avoids crowbar condition and oscillation, such that it is suitable for use with high speed memories in a low-power applications, such as portable computers powered by batteries.
Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.